登入選單
返回Google圖書搜尋
Heterogeneous Built-in Resiliency of Application Specific Programmable Processors
註釋Abstract: "Application Specific Programmable Processors (ASPP) provide efficient implementation for any of k specified functionalities. Using the flexibility provided by multiple functionalities we have developed a novel approach for permanent fault-tolerance called Heterogeneous Built-In-Resiliency (HBIR). The proposed HBIR technique combines the flexibility provided by multiple functionalities with judicious operation-to-operator assignment either to maximize the permanent fault-tolerance of such ASPP designs or to guarantee that the ASPP remains operational in the presence of all possible k-unit faults (for a designer specified k). The proposed multifunctionality based HBIR processor synthesis imposes several unique tasks on the synthesis process: (i) latency determination targeting k-unit fault-tolerance, (ii) application- to-faulty-unit matching and (iii) HBIR scheduling and assignment algorithms. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs."