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Describing Systems for High Level Synthesis in the Verilog Language

Lawrence F. Arnstein

出版	SRC-CMU Research Center for Computer-Aided Design, Pennsylvania SEMATECH Center of Excellence for Rapid Yield Learning, Department of Electrical and Computer Engineering, Carnegie-Mellon University, 1990
URL	http://books.google.com.hk/books?id=50uttgAACAAJ&hl=&source=gbs_api

註釋

Abstract: "In this work, The Verilog Language is used to represent both high and low level models in the System Architect's Workbench. The semantic views of the Verilog Hardware Description Language given by The Verilog Simulator and The Workbench level synthesis system are compared. The goal is to determine to what extent Verilog descriptions can serve as both high level synthesis specifications and simulation models. General conclusions are drawn regarding the reconciliation of the language requirements of simulation and synthesis systems. Additionally, it is shown how structural information found in the high level model is reproduced in the synthesized low level model, maintaining the original design hierarchy.