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Development, Validation, and Application of Semi-Analytical Interconnect Models for Efficient Simulation of Multilayer Substrates
註釋This thesis deals with the development of semi-analytical models for the electrical behavior of vias and traces in chip packages and printed circuit boards. A framework for automated simulation of multilayer structures is also proposed. The validation and evaluation of the models are thoroughly addressed with several test structures and application studies. It is shown that the models can provide good results up to 40 GHz, whereas the numerical efficiency is at least two orders of magnitude higher in comparison to general-purpose numerical methods.