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A Scanline Data Structure Processor for VLSI Geometry Checking

Erik C. Carlson

出版	SRC-CMU Research Center for Computer-Aided Design, Department of Electrical and Computer Engineering, Carnegie-Mellon University, 1987
URL	http://books.google.com.hk/books?id=BEInHQAACAAJ&hl=&source=gbs_api

註釋

The architecture can be viewed as directly interpreting the operators that manipulate the relevant scanline data structures. We show how the edge computations in these two algorithms can be restructured into the form of a single, shared hardware pipeline. Data from a simulation of this processor suggests that, relative to the specific software functions it is intended to replace, the scanline processor can reduce computation time significantly. In particular, simulations of one possible implementation for this processor yield speeds of three orders of magnitude for Manhattan mask data, degrading gracefully to speedups of two orders of magnitude for highly oblique mask data."