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Materials, Devices, and Circuits
出版Woodhead Publishing, 2025-09-01
主題Technology & Engineering / Materials Science / GeneralScience / Physics / Magnetism
ISBN04432473319780443247330
URLhttp://books.google.com.hk/books?id=CX4mEQAAQBAJ&hl=&source=gbs_api
註釋"Ferroelectrics and Negative Capacitance focuses on the materials, devices, and circuit- and system-level applications of ferroelectric devices and technology enabled by newly discovered CMOS process-compatible ferroelectric materials. The book provides in-depth knowledge of the operation of different ferroelectric devices, including their advantages and disadvantages for applications in electronics. Discussion covers not only the fundamental core of the models, but also recent developments and real device effects and techniques to reach compact modeling form for SPICE circuit simulations. The book also covers process variability, device–circuit co-design, and optimization techniques all the way up to the processor level. There is a growing need for a deeper understanding of the physics of ferroelectrics and the negative capacitance effect. Conventional non-volatile memories such as DRAM and flash are now reaching their scaling and performance limits and are unable to provide data rate and low-power requirements for data-intensive applications such as AI. Emerging ferroelectric-based memory devices such as ferroelectric random-access memory (FeRAM), ferroelectric tunnel junction (FTJ), and ferroelectric field-effect transistor (FeFET), promise to mitigate these issues, and have gained traction in the last decade especially due to the discovery of ferroelectricity in CMOS manufacturing process-compatible oxides. At the same time, the scaling and performance of logic devices are also reaching their limit due to limitations imposed by short-channel effects and the inability to remove the generated device heat by reducing the power supply voltage. Ferroelectric-based negative capacitance field-effect transistor (NCFET) technology offers to break the Boltzmann limit of a minimum 60 mV/decade subthreshold swing and provides significant improvements in electrostatic integrity using the negative capacitance property of a ferroelectric layer in its gate stack, thereby enabling the continuation of not only Moore's law but also Dennard's scaling. This book provides an in-depth understanding of ferroelectric logic and memory devices, including polarization switching, domain dynamics, the negative capacitance effect, device operation, compact models of FeRAM, FeFET, FTJ, and NCFET, and device–circuit co-design and optimization for novel NCFET computing.• Analyzes and compares different negative capacitance theories, providing the reader with a clear idea of the most plausible and succinct physical explanations of the effect • Provides detailed modeling of FeRAM, FTJ, FeFET, and various configurations of NCFET (MFIS, MFMIS, Bulk, FinFET, GAA, etc.), including non-ideal effects • Transitions from device-level to circuit-level analysis and eventually to full chip-level/processor-level analysis, which is crucial for system optimization