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Design and Implementation of a Scribe Line Measurement Transistor Test Array Structure in 14nm FinFET CMOS Technology

出版	University of Texas, 2015
URL	http://books.google.com.hk/books?id=LpkUjwEACAAJ&hl=&source=gbs_api

註釋Submicron fin-shaped field effect transistor (FinFET) process technologies pose a variety of challenges for foundries ramping designs into production due to parameter variation. Accurate and relevant electrical transistor parametric data are required to correlate product yield and performance to the process technology throughout the manufacturing cycle. Typically, transistor data are obtained from foundry-designed and isolated transistors test structures which do not resemble the layout, physical attributes, or design style of the transistors in the standard cells of the actual design. As a result, the topographical, density, and stress effects on the transistors of a custom or synthesized design layout are not reflected in the test measurements. To address this issue, a scribe line macro (SLM) test structure with modular transistor arrays utilizing standard cells from the design library was designed for a 14nm FinFET complementary metal oxide semiconductor (CMOS) technology process. The SLM test structure fits in a 52[mu]m by 2000[mu]m footprint and can be printed at multiple locations in the scribe lines of a 300mm wafer. The SLM test structure comprises of four n-type metal oxide semiconductor (NMOS) and four p-type metal oxide semiconductor (PMOS) transistor arrays containing 240 FinFET transistors of 33 types that can be tested rapidly and in parallel. The SLM test structure is designed to generate silicon data for parametric transistor measurements such as I[subscript DSAT], I[subscript DLIN], I[subscript DOFF], V[subscript TSAT], and V[subscript TLIN] using a parametric inline tester in the manufacturing line of a foundry. These silicon measurements will be correlated to simulation data extracted from the netlist of the SLM test structure to eventually improve the 14nm FinFET technology libraries and silicon models. The SLM test structure design will be continuously improved for future technology processes with a goal of enabling accurate and design-relevant transistor parametric measurements to help drive cycle time, cost, and yield improvements