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Manufacturability Aware Routing in Nanometer VLSI
David Z. PanMinsik ChoKun Yuan
出版Now Publishers Inc, 2010-05-04
主題Computers / Logic DesignComputers / Computer EngineeringTechnology & Engineering / GeneralTechnology & Engineering / ElectricalTechnology & Engineering / Electronics / Circuits / VLSI & ULSI
ISBN16019835069781601983503
URLhttp://books.google.com.hk/books?id=NaGJmr_khjoC&hl=&source=gbs_api
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註釋This paper surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical-mechanical polishing, and antenna-effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) as well as construct-by-correction (i.e., post-routing optimization). This paper will provide a holistic view of key design for manufacturability issues in nanometer VLSI routing.