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Design and implementation of RISC I.

University of California, Berkeley. Computer Science DivisionC. H. SequinD. A. Patterson

出版	Computer Science Division, University of California, 1982
URL	http://books.google.com.hk/books?id=P2xLNAAACAAJ&hl=&source=gbs_api

註釋

The Reduced Instruction Set Computer (RISC) is an architecture particularly well suited for implementation as a single-chip VLSI computer. It demonstrates that by a judicious choice of a small set of instructions and the design of a corresponding micro- architecture, one can obtain a machine with high throughput. The limited number of instructions and addressing modes leads to a small control section and to a short machine cycle time. Such a machine also requires a much smaller layout effort and thus leads to a shorter design cycle.