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FPGA-based Filter Bank Implementation for Parallel Digital Signal Processing

Stephan Berner

出版	National Aeronautics and Space Administration, 1999
URL	http://books.google.com.hk/books?id=SLxaAQAACAAJ&hl=&source=gbs_api

註釋

"It may be desired to apply Digital Signal Processing (DSP) to high bandwidth signals with a sampling rate too high for being handled by any commercially available processor. One approach to solve this problem is to divide the spectrum of the signal into subbands by an analysis filter bank, then process the subbands in parallel, and finally, recombine the processed subband signals by a synthesis filter bank. The key point is the fact, that the sampling rate in the subbands can be reduced by downsampling, because the bandwidth of the subband signals is reduced. Figure 1.1 shows this idea. This report describes a hardware implementation of Figure 1.1. The analysis and synthesis filter banks are implemented with Field Programmable Gate Arrays (FPGAs), the subband processing is accomplished with Motorola DSP 56302 Evaluation Modules (EVMs)."--Page 1.