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Minimal Realization for Descriptor Systems
註釋We study minimal realization for descriptor systems with an emphasis on RCL circuits. Minimal realization is related to rank conditions as well as the kernel and the image of a set of matrices (E, A, B, C, D). First, we study topologies of RCL circuits whose matrix representation (E, A, B, C, D) is a minimal realization of its transfer function. If a circuit does not have a minimal matrix representation, we investigate how to eliminate circuit elements (the number of nodes, the number of inductors or voltage sources) and obtain a smaller matrix representation (E, A, B, C, D). Lastly, we propose a numerical algorithm that computes a minimal realization for general descriptor systems. This algorithm can be applied to any descriptor systems, not only to RCL circuits. We also present numerical examples. A minimal realization of an RCL circuit depends on both circuit quantities and circuit topologies. In this dissertation, our interest is restricted to topological characteristics. The previous algorithms on minimal realization reduce the order of (E, A, B, C, D) without changing the matrix D, whereas the numerical algorithm in this dissertation further reduces the order of (E, A, B, C, D) by changing the matrix D.