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VHDL for Designers
註釋12.5. Supplementary test vectors 13. Rapid prototyping 13.1. Introduction 13.1.1. Rapid prototyping 13.2. Real-time kernel--a brief description 13.3. The development system 13.4. Development phases 13.5. Further reading 14. Common design errors in VHDL and how to avoid them 14.1. Signals and variables 14.2. Logic synthesis and sensitivity lists 14.3. Buffers and internal dummy signals 14.4. Declaring vectors with downto or to 14.5. Incompletely defined combinational processes 15. Design examples and design tips 15.1. Adders 15.1.1. One-bit adder with carry in 15.1.2. Eight-bit adder with carry in 15.1.3. Generic adder with carry in 15.1.4. Four-bit vector adder/subtractor 15.2. Vector multiplication 15.3. Resource sharing 15.3.1. Example when resource sharing of an adder is possible 15.3.2. Example when resource sharing of an adder is not possible 15.4. Comparators 15.5. Multiplexors and decoders 15.5.1. Two-to-one multiplexor 15.5.2. Eight-to-one multiplexor 15.5.3. Three-to-eight decoder 15.6. Register 15.6.1. Flip-flop with asynchronous reset 15.6.2. Flip-flop with synchronous reset 15.6.3. Flip-flop with asynchronous reset and set 15.6.4. Eight-bit register with enable and asynchronous reset 15.7. Edge-controlled pulse generator 15.8. Counters 15.8.1. Three-bit counter with enable and carry out 15.8.2. Three-bit up/down counter 15.8.3. Parallel loadable generic up/down counter 15.9. Shift register 15.9.1. Four-bit shift register with serial input data and parallel output data 15.9.2. Four-bit shift register with parallel load and serial output 15.10. Filters 15.10.1. Four-input digital majority-voting filter 15.10.2. Four-input digital addition filter 15.11. Frequency dividers 16. Development tools 16.1. Synopsys 16.1.1. VHDL Compiler and Design Analyzer 16.1.2. Design Ware 16.1.3. Design Compiler 16.1.4. ATPG tools 16.1.5. FPGA Compiler 16.1