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Topological circuit layout

W. M. VanCleemputStanford University Stanford Electronics Laboratories. Digital Systems Laboratory

出版	Stanford Electronics Laboratories, Stanford University, 1976
URL	http://books.google.com.hk/books?id=b-EEAAAAIAAJ&hl=&source=gbs_api

註釋

In this report the topological and geometrical aspects of the circuit layout problem are compared. A circuit layout procedure, based on topological factors, is presented. Whereas most circuit layout procedures are concerned mainly with geometrical aspects, the method described in this report attempts to find a topologically feasible solution to the problem first. From this topological layout, a physical layout is obtained in a second phase. This method can be especially useful for problems where a complete (100%) layout is mandatory. (Author).