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Hardware and Compiler-directed Cache Coherence in Large-scale Multiprocessors
Lynn Choi
Pen-Chung Yew
University of Illinois at Urbana-Champaign. Department of Computer Science
其他書名
Design Considerations and Performance Study
出版
Department of Computer Science, University of Illinois at Urbana-Champaign
, 1996
URL
http://books.google.com.hk/books?id=dx4nD8DjYT4C&hl=&source=gbs_api
註釋
Abstract: "In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors, such as the Cray T3D. The scheme can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is minimal and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data flow analysis, have been implemented on the Polaris parallelizing compiler [33]. From our simulation study using the Perfect Club benchmarks [5], we found that in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. Given its comparable performance and reduced hardware cost, the proposed scheme can be a viable alternative for large-scale multiprocessors such as the Cray T3D, which rely on users to maintain data coherence."
