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Power Microelectronics
Yung C. Liang
Ganesh S. Samudra
其他書名
Device and Process Technologies
出版
World Scientific
, 2009
主題
Technology & Engineering / Electrical
Technology & Engineering / Electronics / General
Technology & Engineering / Electronics / Microelectronics
Technology / Engineering / Electrical
ISBN
9812791000
9789812791009
URL
http://books.google.com.hk/books?id=kJIsPQAACAAJ&hl=&source=gbs_api
註釋
Table of Contents Acknowledgement V 1 Introduction 1 2 Carrier Physics and Junction Electrostatics 3 2.1 Introduction 3 2.2 Crystal Structure and Energy Bands 3 2.3 Carrier Concentration and Fermi Level 10 2.3.1 Intrinsic Semiconductor 13 2.3.2 Extrinsic Semiconductor 15 2.4 Carrier Transport 17 2.4.1 Carrier Drift 18 2.4.2 Carrier Diffusion 23 2.4.3 Resistivity 24 2.5 Bandgap Reduction 25 2.6 Carrier Recombination 29 2.6.1 Carrier Lifetime 34 2.6.2 Carrier Lifetime Control 36 2.6.3 Auger Recombination 44 2.7 Basic Equations in Semiconductor 45 2.8 p-n Junction Electrostatics 47 2.9 Junction Breakdown Phenomena 51 2.9.1 Abrupt p+-n Junction 55 2.9.2 Linearly Graded Junction 57 2.10 Punchthrough Phenomenon 59 2.11 Junction Termination 62 2.11.1 Cylindrical Junction 63 2.11.2 Spherical Junction 65 2.11.3 Floating Field Ring 66 2.11.4 Etched Contour Termination 68 2.11.5 Bevelled Edge Termination 69 2.11.6 Field Plate 72 2.11.7 Junction Termination Extension 72 2.11.8 SIPOS (Semi-insulating Polycrystalline Silicon) Termination 73 2.12 Summary 74 3 Bipolar Junction Diode 78 3.1 Introduction 78 3.2 Basic Junction Diode Theory 81 3.2.1 Forward Conduction 81 3.2.2 Short-base Diode 83 3.2.3 Junction Capacitance 85 3.3 High-Voltage p+-n--n+ Diode 87 3.3.1 Forward Conduction 88 3.3.2 Reverse Blocking 95 3.3.3 Temperature Effect 96 3.4 Schottky Barrier Diode 103 3.4.1 Forward Conduction 106 3.4.2 Reverse Blocking 109 3.5 Ohmic Contact 111 3.6 GaAs and SiC Power Diodes 114 3.7 Switching Characteristics 119 3.7.1 Turn-on Transient 120 3.7.2 Turn-off Transient 123 3.8 MPS (Merged p-i-n/Schottky) Diode 127 3.9Smart-Power Integrated Synchronous Rectifier 128 3.10 Summary 136 4 Power Metal-Oxide-Semiconductor Field-Effect Transistor 141 4.1 Introduction 141 4.2 Basic MOS Physics 142 4.2.1 Flat-band State 144 4.2.2 Accumulation State 144 4.2.3 Depletion State 144 4.2.4 Inversion State 146 4.2.5 MOS Capacitance 147 4.2.6 Threshold Voltage 149 4.3 Static Characteristics 151 4.3.1 Linear Region Operation 154 4.3.2 Saturation Region Operation 157 4.3.3 Mobility Degradation 158 4.3.4 Forward Blocking 159 4.4 Switching Characteristics 159 4.4.1 Turn-on Transient 159 4.4.2 Turn-off Transient 162 4.4.3 Gate Charge 165 4.4.4 High-frequency Operation 166 4.4.5 Parasitic Body Diode 167 4.5 dv/dt Limit 167 4.6 Dummy-Gated Structure 169 4.7 Folded Gate Structure 171 4.8 Lateral Radio Frequency (RF) Power MOSFET 172 4.8.1 Graded Gate 173 4.8.2 Stepped Lateral Double Diffusion 174 4.8.3 Partial Silicon-on-Insulator Platform 175 4.8.4 Partial SOI Platform Formation 177 4.9 Parallel and Series Operations 180 4.10 Gate Drive Circuits 183 5 Insulated-Gate Bipolar Transistor 189 5.1 Introduction 189 5.2 Device Structure and Current-Voltage Characteristics 191 5.2.1 Forward Conduction Characteristics 193 5.2.2 Output Resistance 197 5.3 Switching Characteristics 198 5.4 Latch-up 200 5.5 Temperature Effects 203 5.6 Series and Parallel Operations 204 5.7 Device Operations under Soft-switching 205 5.7.1 Dual-Gate IGBT for ZV Soft-Switching 207 5.8 Lateral IGBT Structure 209 5.9 Integrated Current Sensor 211 5.9.1 Fabrication Aspects 215 5.9.2 Performances 216 5.10 Safe Operating Area 221 5.11 Overcurrent Protection 222 5.12 Vertical IGBT Fabrication Process 229 5.13 Related MOS-Bipolar Structures 230 5.13.1 Emitter Switched Thyristor (EST) 230 5.13.2 Base-Resistance-Controlled Thyristor (BRT) 238 5.13.3 Injection-Enhanced Insulated-Gate Bipolar Transistor (IEGT) 243 5.13.4 MOS-Controlled Thyristor (MCT) 243 6 Superjunction Structures 248 6.1 Introduction 248 6.2 The Unipolar Ideal Silicon Limit 249 6.3 The Superjunction Structure 252 6.3.1 SJ Electric Field Profiles 257 6.3.2 Charge Imbalance 259 6.3.3 Fabrication Technologies 259 6.4 Practical SJ Performance 263 6.4.1 The Practical Concentration Equation 274 6.4.2 Practical SJ Performance Equation 276 6.5 Polysilicon Flanked VDMOS (PF VDMOS) 277 6.6 Oxide Bypassed (OB)SJ MOSFET 280 6.7 Graded Doping in Drift Region 288 6.8 Tunable Oxide Bypassed MOSFETs 290 6.9 Gradient Oxide Bypassed (GOB) Structure 297 6.10 Lateral Superjunction Power MOSFET 301 6.10.1 Device Process Technology 304 7 Fabrication and Modeling of Power Devices 310 7.1 Unit Process Steps 310 7.1.1 Lithography 310 7.1.2 Etching 313 7.1.3 Deposition 314 7.1.4 Oxidation 315 7.1.5 Ion Implantation 318 7.1.6 Epitaxy 323 7.1.7 Diffusion 323 7.2 Basic Models for the Simulation of Unit Process Steps 326 7.2.1 Thermal Oxidation Models 326 7.2.2 Diffusion Models 328 7.2.3 Ion Implantation Models 329 7.2.4 Optical Lithography 330 7.2.5 Etching 332 7.2.6 Deposition 333 7.3 Advances in the Processes for Power Devices 333 7.3.1 Modifications to Improve Gate Oxide Reliability and Breakdown Performance 333 7.3.2 Use of Selective Epitaxial Growth for Performance Enhancement 336 8 Practical Case Studies in Power Devices 340 8.1 Case Study I Process Integration and Design Of PFVDMOS 340 8.1.1 Process Integration to Implement PFVDMOS Device 341 8.1.2 Simulation and Process Parameter Determination of PFVDMOS Device 344 8.1.3 Experimental Results 358 8.2 Case Study 2 Tunable Oxide Bypassed MOSFETS 373 8.2.1 100 V TOBUMOS Fabrication 374 8.2.2 Simulation on 100V TOBUMOS 375 8.2.3 Process Flow and Cross-Sections 377 8.2.4 Key Precautions in TOBUMOS Fabrication 386 8.2.5 Device Structure and Mask Layout Design 390 8.2.6 Mask Floorplan and Splits for 100V TOBUMOS Fabrication 394 8.2.7 100V TOBUMOS Measurement Results and Discussions 396 8.2.8 Investigations for Off-State Failure 403 8.2.9 Measurement Results on New Modified TOBUMOS Fabrication 407 Index 411
