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An O(n) Algorithm for Transistor Stacking with Performance Constraints

Bulent Basaran

出版	Center for Electronic Design Automation, Carnegie Mellon University, 1995
URL	http://books.google.com.hk/books?id=m1IItwAACAAJ&hl=&source=gbs_api

註釋

Abstract: "We describe a new constraint-driven stacking algorithm for diffusion area minimization of CMOS circuits. It employs an Eulerian trail finding algorithm that can satisfy analog-specific performance constraints. Our technique is superior to other published approaches both in terms of its time complexity and in the optimality of the stacks it produces. For a circuit with n transistors, the time complexity is O(n). All performance constraints are satisfied and, for a certain class of circuits, optimum stacking is guaranteed."