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Timing Skew Calibration for Time Interleaved Analog to Digital Converters

Luke Wang

出版	University of Toronto, 2014
URL	http://books.google.com.hk/books?id=pL8GuAEACAAJ&hl=&source=gbs_api

註釋

This thesis presents a novel background timing skew calibration method used to improve the dynamic performance of time-interleaved analog-to-digital converters. A prototype 10GS/s 8bit 80-way time-interleaved SAR ADC was designed and fabricated in 65nm CMOS to illustrate this concept. The performance of a subset 5GS/s ADC is reported due to inadequate delay buffer range. After calibration, the 5GS/s ADC achieves an SNDR of 33.3dB at Nyquist and consumes 138.6mW from a 1V supply, yielding an FOM of 738fJ/conv-step.