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CMOS Image Sensor Design for Always-on Object Detection

出版	Stanford University, 2019
URL	http://books.google.com.hk/books?id=rO8iygEACAAJ&hl=&source=gbs_api

註釋Object detection is an important vision task in embedded systems like smartphones, real-time monitoring devices, and augmented reality. A standard approach is to embed a CMOS image sensor with a backend detection algorithm. Deep neural networks (DNNs) are currently the best-performing algorithms for such applications and there has been extensive work on improving the efficiency of algorithms and hardware. Despite these efforts, customized DNN ASICs are relatively energy-hungry due their large computational footprint. Therefore, to achieve efficient object detection in an embedded device, it is attractive to consider less complex, prior-art algorithms that use low-complexity hand-crafted features as a wakeup for a more powerful DNN. For instance, histograms of oriented gradients (HOGs) present a good tradeoff between computational requirements and detection accuracy. To optimize the wakeup detector for always-on functionality, we can build the feature-extraction directly into the CMOS image sensor. Towards this end, this dissertation presents an application-optimized QVGA image sensor for low-power, always-on object detection using HOGs. In contrast to conventional CMOS imagers that feature linear and high-resolution ADCs, this readout scheme extracts logarithmic intensity gradients at 1.5 or 2.75 bits of resolution. This eliminates unnecessary illumination-related data and allows the HOG feature descriptors to be compressed by up to 25x relative to a conventional 8-bit readout. As a result, the digital backend detector, which typically limits system efficiency, incurs less data movement and computation, leading to an estimated 3.3x energy reduction. The imager employs a column-parallel readout with analog cyclic-row buffers that also perform arbitrary-sized pixel-binning for multi-scale object detection. The log-digitization of pixel gradients is realized by using a ratio-to-digital converter, which performs successive capacitive divisions to its input voltages. The prototype IC was fabricated in a 0.13 um CIS process with standard 4-T, 5 um pixels and consumes 99 pJ/pixel. The power consumption is comparable to conventional low-power designs showing there is little energy overhead in the novel readout. Experiments using a deformable parts model detector for three object classes (persons, bicycles and cars) indicate detection accuracies that are on par with conventional systems.