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A Modular Inversion Hardware Algorithm with a Redundant Binary Representation

Kyōto Daigaku. Joho Kogaku KyoshitsuN. Takagi

出版	Department of Information Science, Faculty of Engineering, Kyoto University, 1992
URL	http://books.google.com.hk/books?id=tt-8GwAACAAJ&hl=&source=gbs_api

註釋Abstract: "A hardware algorithm for modular inversion is proposed. It is based on the extended Euclidean algorithm. All intermediate results are represented in a redundant binary representation with a digit set [0,1,-1]. All addition/subtractions are performed without carry propagation. A modular inversion is carried out in O(n) clock cycles where n is the word length of the modulus. The length of each clock period is a constant independent of n. A modular inverter based on the algorithm has a regular cellular array structure with a bit slice feature and is very suitable for VLSI implementation. Its amount of hardware is proportional to n."