登入選單
返回Google圖書搜尋
ASIC and FPGA Verification
Richard Munden
其他書名
A Guide to Component Modeling
出版Elsevier, 2004-10-23
主題Computers / Data Science / Data Modeling & DesignTechnology & Engineering / Electronics / Circuits / Integrated
ISBN00804759229780080475929
URLhttp://books.google.com.hk/books?id=wXtxZNZUWq8C&hl=&source=gbs_api
EBookSAMPLE
註釋Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.*Provides numerous models and a clearly defined methodology for performing board-level simulation.*Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.