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High Throughput Iterative Decoders:
Engling YeoBorivoje Nikolic
其他書名
Towards Shannon Bound in VLSI
出版Springer US, 2008-12-15
主題Technology & Engineering / TelecommunicationsTechnology & Engineering / Electronics / Circuits / GeneralComputers / Information TheoryTechnology & Engineering / ElectricalLanguage Arts & Disciplines / Library & Information Science / General
ISBN14020766499781402076640
URLhttp://books.google.com.hk/books?id=zjgfkgEACAAJ&hl=&source=gbs_api
註釋High Throughput Iterative Decoders: Towards Shannon Bound in VLSI addresses the algorithms and implementations of iterative decoders for error control in communication applications. The iterative codes are based on various concatenated schemes of convolutional codes, also known as turbo codes, and low density parity check (LDPC) codes. The decoding alogirthms are instances of message passing or belief propagation algorithms, which rely on the iterative cooperation between soft-decoding modules known as soft-input-Iterative decoding is a recent advacement in communication theory that is applicable to wireless, wireline, and optical communicatiosn systems. It promises significant advantage in bit-error rate (BER) performance at signal to noise ratios very close to the theoretical capacity bound. However, a direct mapping of the decoding algorithms leads to a multifold increase in the implementation complexity. As deep submicron technology matures, there is a possibility of implementing these applications that were once thought to be too complex to fit onto a single silicon die. We present the architectural and implementation issues related to the VLSI implementation of high throughput iterative decoders. The computational hardware and memory requirements of different competing architectures are discussed. This monograph also introduces reduced complexity modifications of algorithms that provide efficient mapping into architectures and VLSI implementations.